The present invention relates to a phase synchronization circuit, and more in particular, to a phase synchronization circuit suitable for producing an output timing pulse in phase with an input pulse signal, with the phase thereof delayed and advanced alternatively like a read data signal of a magnetic recording apparatus.
In a magnetic recording apparatus such as a magnetic disk unit or a magnetic tape unit, a phase sync circuit like the one shown in FIG. 10 is generally used to produce a timing signal in phase with the data read out of a recording medium. The phase sync circuit shown in FIG. 10 is required to comprise a frequency-following function for meeting the frequency variations of a read data signal DTIN attributable to a change in the feed rate of the recording medium, source voltage or ambient temperature, and also to comprise a jitter suppression characteristic for coping with instantaneous timing variations caused by pattern peak shifts or noises. As a result, a conventional phase sync circuit comprises a phase comparator 10 for detecting the phase difference between a read data signal DTIN and an output signal VCOOUT of the phase sync circuit, a low-pass filter 20 for smoothing the phase difference signal thus detected and producing a DC signal "A" proportional to the phase difference, and a voltage-controlled oscillator (VCO) for producing an output signal VCOOUT with the oscillation frequency controlled by the DC signal A.
Now, the operation of a conventional circuit shown in FIG. 10 will be explained. When the output signal VCOOUT is delayed from the phase of a read data signal DTIN, for example, a delayed phase difference is detected by the phase comparator 10, and the voltage of the DC phase difference signal A produced from the low-pass filter 20 is increased. The voltage increase of the DC signal A increases the oscillation voltage of the voltage-controlled oscillator 30, and the resulting increase in the oscillation frequency advances and corrects the phase of the output signal VCOOUT.
When the phase of the output signal VCOOUT is advanced from the read data signal DTIN, on the other hand, the phase comparator 10 detects an advanced phase difference which in turn reduces the voltage of the AC signal A. This decrease in the voltage of the DC signal A decreases the oscillation voltage of the voltage-controlled oscillator 30 for a reduced oscillation frequency, thus correcting by delaying the phase of the output signal VCOOUT. Usually, in the absence of a peak shift of the read data signal DTIN, delayed or advanced phase differences are continuously detected at the time of phase correction of a phase sync circuit, so that the phase difference is gradually reduced until the sync process is completed with the phase difference eliminated. Also, when synchronization with the read data signal DTIN is to be attained from a free-running state of the voltage-controlled oscillator 30, the low-pass filter 20 is controlled to a high-speed sync responding state by a signal FS in order to complete the sync process within a short time, and upon completion of the sync process, it is controlled to a low-speed sync responding state in order to maintain a steady operation.
The phase sync circuit of this type has a jitter suppression characteristic against an instantaneous peak shift of the read data ocurring every several or several tens of read data pulses, for example. As disclosed in JP-A-59-165209 and JP-A-59-178608, however, such a circuit fails to take into consideration the magnetic recording characteristic in which peak shifts of phase delay and advance occur alternately due to a predetermined amount of distortion or the like of a read waveform.
The disclosures in JP-A-59-165209 and JP-A-59-178608 are also related to the present invention. Specifically, JP-A-59-165209 discloses an invention for improving a case of alternate phase delay and advance by correcting the read waveform itself with an analog technique using a delay line, an attenuator or the like and thus reducing the peak shift of the read data as far as possible. In the circuit disclosed by JP-A-59-178608, on the other hand, a peak shift of alternate phase delay and advance is minimized by a cancel circuit to prevent the output of a phase comparator from being supplied to a voltage-controlled oscillator.
The conventional phase sync circuit shown in FIG. 10 fails to take into consideration the peak shifts with alternate phase delay and advance caused by the magnetic recording characteristic as mentioned above. This would not pose any problem as long as the recording density remains low because the long intervals of read data pulses makes the amount of the peak shifts negligible. With the rapid increase in data transfer speed and recording density, however, this problem has become one of the most important considerations in a phase sync circuit and is not negligible.
As described above methods of solving this problem are disclosed in JP-A-59-165209 and JP-A-59-78608. The method of JP-A-59-165209, however, is mainly aimed at symmetry of a read data waveform and fails to provide an effective means for solving the above-mentioned problem by completely eliminating the amount of peak shift. JP-A-59-178608, on the other hand, fails to take into consideration a case of frequent peak shifts with alternate phase advance and delay or, especially, the error which may occur between the rotational speed of each of a plurality of recording media connected to a single phase sync circuit and the free-running frequency of a voltage-controlled oscillator in the phase sync circuit in a large magnetic disk apparatus. More specifically, in the case where a peak shift of phase advance and delay occurs frequently (Such peak shift is frequent in many cases although the amount of shift varies as it is caused by the magnetic recording characteristic), the phase comparator 10 shown in FIG. 10 cannot detect the phase difference, and therefore the low-pass filter 20 produces 0 V as a DC signal A. The oscillation voltage of the voltage-controlled oscillator 30 thus becomes about 0 V, and the oscillation frequency thereof returns to the free-running frequency. As a result, an error of frequency or phase of the read data is impossible to correct or the fluctuations of the output of the voltage-controlled oscillator 30 around the free-running frequency reduces the phase-correcting ability.
Also, if a plurality of rotary recording media are used in connection, the variations in the rotational speed between them increases the difference between the free-running frequency of the voltage-controlled oscillator 30 and the rotational speed of the recording media, thus making it impossible to correct the phase and frequency from the very beginning.